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PI7C7300 Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation |
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PI7C7300 Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation |
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8 / 109 page  PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 8 OF 109 09/25/03 Revision 1.09 14.1.44 SECONDARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 8Ch .......................................................................................................................................... 89 14.1.45 PRIMARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 90h ............... 89 14.1.46 PRIMARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 94h.............. 89 14.1.47 PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER – OFFSET 98h .... 90 14.1.48 PRIMARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 9Ch.. 90 14.1.49 CAPABILITY ID REGISTER – OFFSET B0h .................................................................. 90 14.1.50 NEXT POINTER REGISTER – OFFSET B0h .................................................................. 90 14.1.51 SLOT NUMBER REGISTER – OFFSET B0h................................................................... 91 14.1.52 CHASSIS NUMBER REGISTER – OFFSET B0h............................................................. 91 14.1.53 CAPABILITY ID REGISTER – OFFSET C0h .................................................................. 91 14.1.54 NEXT POINTER REGISTER – OFFSET C0h.................................................................. 91 14.1.55 HOT SWAP CONTROL AND STATUS REGISTER – OFFSET C0h ............................... 91 15 BRIDGE BEHAVIOR.................................................................................................................... 92 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES ............................................................... 92 15.2 TRANSACTION ORDERING .................................................................................................... 93 15.3 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)..................................... 93 15.3.1 MASTER ABORT.................................................................................................................. 93 15.3.2 PARITY AND ERROR REPORTING.................................................................................... 93 15.3.3 REPORTING PARITY ERRORS........................................................................................... 94 15.3.4 SECONDARY IDSEL MAPPING ......................................................................................... 94 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ............................................................... 94 16.1 BOUNDARY SCAN ARCHITECTURE..................................................................................... 95 16.1.1 TAP PINS.............................................................................................................................. 95 16.1.2 INSTRUCTION REGISTER.................................................................................................. 95 16.2 BOUNDARY-SCAN INSTRUCTION SET ................................................................................ 96 16.3 TAP TEST DATA REGISTERS .................................................................................................. 97 16.4 BYPASS REGISTER ................................................................................................................... 97 16.5 BOUNDARY-SCAN REGISTER................................................................................................ 97 16.6 TAP CONTROLLER ................................................................................................................... 97 17 ELECTRICAL AND TIMING SPECIFICATIONS................................................................. 100 17.1 MAXIMUM RATINGS ............................................................................................................. 101 17.2 3.3V DC SPECIFICATIONS ..................................................................................................... 101 17.3 3.3V AC SPECIFICATIONS ..................................................................................................... 102 17.4 PRIMARY AND SECONDARY BUSES AT 66MHZ CLOCK TIMING ................................. 103 17.5 PRIMARY AND SECONDARY BUSES AT 33MHZ CLOCK TIMING ................................. 103 17.6 POWER CONSUMPTION ........................................................................................................ 103 18 272-PIN PBGA PACKAGE FIGURE ........................................................................................ 104 18.1 PART NUMBER ORDERING INFORMATION...................................................................... 104 APPENDIX A: PI7C7300A EVALUATION BOARD USER’S MANUAL....................................... 105 FREQUENTLY ASKED QUESTIONS ................................................................................................. 107 LIST OF TABLES TABLE 4-1 PCI TRANSACTIONS .............................................................................................................. 21 TABLE 4-2 WRITE TRANSACTION FORWARDING .............................................................................. 23 TABLE 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES................................... 26 TABLE 4-4 READ PREFETCH ADDRESS BOUNDARIES....................................................................... 27 |
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