 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PI7C7300A Datasheet(PDF) 11 Page - Pericom Semiconductor Corporation |
|
||||||||||||||||||||||||||||||
PI7C7300A Datasheet(HTML) 11 Page - Pericom Semiconductor Corporation |
|
|
11 / 109 page  PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 11 OF 109 09/25/03 Revision 1.09 1 INTRODUCTION PRODUCT DESCRIPTION The PI7C7300A is Pericom Semiconductor’s second-generation PCI-PCI Bridge. It is designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C7300A supports only synchronous bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the Secondary Buses operating at either 33MHz or 66MHz. The Primary and Secondary Buses can also operate in concurrent mode, resulting in added increase in system performance. Concurrent bus operation off-loads and isolates unnecessary traffic from the Primary Bus; thereby enabling a master and a target device on the same Secondary PCI Bus to communicate even while the Primary Bus is busy. In addition, the Secondary Buses have load balancing capability, allowing faster devices to be isolated away from slower devices. Among the other features supported by the PI7C7300A are: support for up to 15 devices on the Secondary Buses, Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support and Dual Addressing Cycle. PRODUCT FEATURES • 32-bit Primary and Two Secondary Ports run up to 66MHz • All 3 ports compliant with the PCI Local Bus Specification, Revision 2.2 • Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. - All I/O and memory commands - Type 1 to Type 0 configuration conversion - Type 1 to Type 1 configuration forwarding - Type 1 configuration write to special cycle conversion • Concurrent Primary to Secondary Bus operation and independent intra-Secondary Port channel to reduce traffic on the Primary Port • Provides internal arbitration for one set of eight secondary bus masters (S1 bus) and one set of seven (eight if Hot Swap is disable)secondary bus masters (S2 bus) - Programmable 2-level priority arbiter - Disable control for use of external arbiter • Supports posted write buffers in all directions • Three 128 byte FIFO’s for delay transactions • Three 128 byte FIFO’s for posted memory transactions • Enhanced address decoding - 32-bit I/O address range - 32-bit memory-mapped I/O address range - VGA addressing and VGA palette snooping - ISA-aware mode for legacy support in the first 64KB of I/O address range • Dual Addressing cycle (64-bit) • Interrupt handling - PCI interrupts are routed through an external interrupt concentrator • Supports system transaction ordering rules • Tri-state control of output buffers on secondary buses • Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support • Industrial Temperature range –40°C to 85°C • IEEE 1149.1 JTAG interface support • 3.3V core; 3.3V PCI I/O interface with 5V I/O tolerance • 272-pin plastic BGA package |
Similar Part No. - PI7C7300A |
|
Similar Description - PI7C7300A |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
