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DLP2000FQC Datasheet(PDF) 4 Page - Texas Instruments |
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DLP2000FQC Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 40 page  4 DLP2000 DLPS078 – JULY 2017 www.ti.com Product Folder Links: DLP2000 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH (mm) NAME NO. LOADB K10 Input LVCMOS DDR Parallel Latch Load Enable. 7.64 SCTRL K12 Input LVCMOS DDR Serial Control (Sync). 8.62 DRC_BUS K14 Input LVCMOS Reset Control Serial Bus. Synchronous to Rising Edge of DCLK. Bond Pad does Not connect to internal Pull Down 7.28 DRC_OEZ K18 Input LVCMOS Active Low. Output Enable signal for internal Reset Driver circuitry. Bond Pads do Not connect to internal Pull Down 4.69 DRC_STROBE J15 Input LVCMOS Rising Edge on DRC_STROBE latches in the Control Signals. Synchronous to Rising Edge of DCLK. Bond Pad does Not connect to internal Pull Down 7.61 SAC_BUS K16 Input LVCMOS Stepped Address Control Serial Bus. Synchronous to Rising Edge of DCLK. Bond Pad does Not connect to internal Pull Down 8.17 SCAN_TEST K20 Input LVCMOS MUX’ed output for scanned chip id 1.18 POWER VBIAS J16 Power Power supply for Positive Bias level of Mirror Reset signal VOFFSET K15 Power Power Supply for High Voltage CMOS logic. Power Supply for Stepped High Voltage at Mirror Address Electrodes. Power supply for Offset level of Mirror Reset signal VRESET J20 Power Power supply for Negative Reset level of Mirror Reset signal VCC J1 Power Power Supply for Low Voltage CMOS logic. Power Supply for Normal High Voltage at Mirror Address Electrodes. Power supply for Offset level of Mirror Reset signal during Power Down VCC J11 Power VCC J21 Power VCC K1 Power VCC K11 Power VCC K21 Power VSS J3 Power Common return. Ground for all power. VSS J5 Power VSS J9 Power VSS J14 Power VSS J17 Power VSS J18 Power VSS J19 Power VSS K3 Power VSS K5 Power VSS K8 Power VSS K13 Power VSS K17 Power VSS K19 Power |
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