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DRA780BDGABFRQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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DRA780BDGABFRQ1 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 273 page  4 DRA780, DRA781, DRA782 DRA783, DRA786, DRA787 SPRS975C – AUGUST 2016 – REVISED JULY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: DRA780 DRA781 DRA782 DRA783 DRA786 DRA787 Table of Contents Copyright © 2016–2017, Texas Instruments Incorporated Table of Contents 1 Device Overview ......................................... 1 1.1 Features ............................................. 1 1.2 Applications ........................................... 2 1.3 Description ............................................ 2 1.4 Functional Block Diagram ........................... 3 2 Revision History ......................................... 5 3 Device Comparison ..................................... 6 3.1 Device Comparison Table ............................ 6 4 Terminal Configuration and Functions .............. 8 4.1 Pin Diagram .......................................... 8 4.2 Pin Attributes ......................................... 8 4.3 Signal Descriptions .................................. 39 4.4 Pin Multiplexing ..................................... 65 4.5 Connections for Unused Pins ....................... 76 5 Specifications ........................................... 77 5.1 Absolute Maximum Ratings ......................... 77 5.2 ESD Ratings ........................................ 78 5.3 Power on Hour (POH) Limits ........................ 78 5.4 Recommended Operating Conditions ............... 79 5.5 Operating Performance Points ...................... 80 5.6 Power Consumption Summary ...................... 90 5.7 Electrical Characteristics ............................ 90 5.8 Thermal Characteristics ............................. 96 5.9 Timing Requirements and Switching Characteristics ....................................... 97 6 Detailed Description .................................. 172 6.1 Description ......................................... 172 6.2 Functional Block Diagram ......................... 172 6.3 DSP Subsystem ................................... 173 6.4 IPU ................................................. 178 6.5 EVE ................................................ 179 6.6 Memory Subsystem ................................ 181 6.7 Interprocessor Communication .................... 184 6.8 Interrupt Controller ................................. 185 6.9 EDMA .............................................. 185 6.10 Peripherals ......................................... 187 6.11 On-Chip Debug .................................... 199 7 Applications, Implementation, and Layout ...... 203 7.1 Introduction ........................................ 203 7.2 Power Optimizations ............................... 204 7.3 Core Power Domains .............................. 215 7.4 Single-Ended Interfaces ........................... 224 7.5 Differential Interfaces .............................. 227 7.6 Clock Routing Guidelines .......................... 228 7.7 DDR2 Board Design and Layout Guidelines ....... 228 7.8 DDR3 Board Design and Layout Guidelines ....... 240 7.9 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing ........................................ 263 8 Device and Documentation Support .............. 265 8.1 Device Nomenclature .............................. 265 8.2 Tools and Software ................................ 267 8.3 Documentation Support ............................ 267 8.4 Receiving Notification of Documentation Updates . 268 8.5 Related Links ...................................... 268 8.6 Community Resources ............................. 269 8.7 Trademarks ........................................ 269 8.8 Electrostatic Discharge Caution ................... 269 8.9 Export Control Notice .............................. 269 8.10 Glossary ............................................ 269 9 Mechanical Packaging and Orderable Information ............................................. 270 9.1 Mechanical Data ................................... 270 |
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