HM62864 Series

10

Write Cycle

HM62864-5

HM62864-7

HM62864-8

Parameter

Symbol Min

Max

Min

Max

Min

Max

Unit

Notes

Write cycle time

t

WC

55

—

70

—

85

—

ns

Chip selection to end of write

t

CW

50

—

60

—

75

—

ns

4

Address setup time

t

AS

0

—

0

—

0

—

ns

5

Address valid to end of write

t

AW

50

—

60

—

75

—

ns

Write pulse width

t

WP

40

—

50

—

55

—

ns

3, 8

Write recovery time

t

WR

0

—

0

—

0

—

ns

6

Write to output in high-Z

t

WHZ

0

20

0

25

0

30

ns

1, 2, 7

Data to write time overlap

t

DW

30

—

30

—

35

—

ns

Data hold from write time

t

DH

0

—

0

—

0

—

ns

Output active from end of write

t

OW

5

—

5

—

5

—

ns

2

Output disable to output in high-Z

t

OHZ

0

20

0

25

0

30

ns

1, 2, 7

Notes: 1. t

and are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap of a low

CS1, a high CS2 and a low WE. A write begins at

the latest transition among

CS1 going low, CS2 going high, and WE going low. A write ends at

the earliest transition among

CS1 going high, CS2 going low, and WE going high. t

measured from the beginning of write to the end of write.

4. t

5. t

6. t

cycle.

7. During this period, I/O pin are in the output state; therefore, the input signals of the opposite

phase to the outputs must not be applied.

8. In the write cycle with

OE low fixed, t

of data bus contention, t