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M61538FP Datasheet(PDF) 5 Page - Hitachi Semiconductor |
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M61538FP Datasheet(HTML) 5 Page - Hitachi Semiconductor |
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5 / 12 page  M61538FP Rev.1.0, Mar.23.2004, page 5 of 11 Clock and Data Timings tWHC tcr 25% 75% LATCH tWLC tf tr tHLD tSHD tHHD tSLD tHLD (D0 ~ D15) tSLD DATA CLOCK 50% 25% 75% Timing Definition of Digital Block Limits Parameter Symbol Min Typ Max Units CLOCK cycle time tcr 8 — — CLOCK pulse width (“H” level) tWHC 3.2 — — CLOCK pulse width (“L” level) tWLC 3.2 — — Rising time of clock and data tr — — 0.8 Falling time of clock and data tf — — 0.8 µs DATA setup time (Rising time of clock) tSHD 1.6 — — DATA setup time (Falling time of clock) tSLD 1.6 — — DATA hold time (“H” level) tHHD 1.6 — — DATA hold time (“L” level) tHLD 1.6 — — |
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