Low-Power, Compact 2.5Gbps or 2.7Gbps

Clock-Recovery and Data-Retiming IC

_______________________________________________________________________________________

3

AC ELECTRICAL CHARACTERISTICS

noted.) (Note 4)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

RATESET = low

2.488

Serial Input Data Rate

RATESET = high

2.67

Gbps

Clock-to-Q Delay

Figure 2 (Note 5)

-70

+70

ps

Jitter Peaking

f

≤ 2MHz

0.1

dB

Jitter Transfer Bandwidth

RATESET = Low

2.0

MHz

f = 70kHz, 0.4UI deterministic jitter

on input data

6.9

f = 100kHz, 0.4UI deterministic jitter

on input data

2.12

4.5

f = 1MHz, 0.4UI deterministic jitter

on input data

0.33

0.6

(Notes 6, 8)

f = 10MHz, 0.4UI deterministic jitter

on input data

0.15

0.3

f = 70kHz, 0.4UI deterministic jitter

on input data

6.9

f = 100kHz, 0.4UI deterministic jitter

on input data

2.12

4.5

f = 1MHz, 0.4UI deterministic jitter

on input data

0.33

0.6

Sinusoidal Jitter Tolerance

(Notes 6, 9)

f = 10MHz, 0.37UI deterministic jitter

on input data

0.15

0.3

5

6.8

(Notes 7, 8)

45

62

6

7.65

Jitter Generation

(Notes 7, 9)

40

86

Clock Output Edge

Speed

20% to 80%

60

110

ps

Data Output Edge

Speed

20% to 80%

60

110

ps

Tolerated Consecutive

Identical Digits

2000

bits

100kHz to 2.5GHz

17

SDI± Input Return Loss

(-20log(

2.5GHz to 4.0GHz

14

dB

Frequency Acquisition

Time

Figure 4

1

ms

µs

LOL Assert Time

Figure 4

1.6