SN65MLVD201, SN65MLVD203

SN65MLVD206, SN65MLVD207

SLLS558A – DECEMBER 2002 – JUNE 2003

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7

Output

A/Y

Output

tpLH

tpHL

Input

C3

0.5 pF

B/Z

D

0 V

0.9V

V

0 V

tf

tr

VCC

VCC/2

0 V

SS

SS

0 V

0.1V

SS

SS

C1

1 pF

C2

1 pF

VP(H)

VP(L)

R1

50

Ω

NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz,

duty cycle = 50

± 5%.

B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are

±20%.

C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.

D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

A/Y

B/Z

R1

24.9

Ω

tpZH

tpHZ

tpZL

tpLZ

VCC

VCC/2

0 V

∼ 0.6 V

0.1 V

0 V

∼ –0.6 V

0 V

–0.1 V

DE

Output With

D at VCC

Output

0 V or VCC

DE

Output With

D at 0 V

C1

1 pF

R2

24.9

Ω

C4

0.5 pF

C2

1 pF

D

C3

2.5 pF

NOTES:A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 500 kHz, duty cycle = 50 ±

5%.

B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are

±20%.

C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.

D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.

Figure 6. Driver Enable and Disable Time Circuit and Definitions