Electronic Components Datasheet Search
Selected language     English  ▼


TRBUG1CFBC000E2G Datasheet(PDF) 5 Page - OPLINK Communications Inc.

Part No. TRBUG1CFBC000E2G
Description  Multi-rate Gigabit & Fast Ethernet Transceivers Bi-Directional SFP 1000BASE 10KM LC Receptacle
Download  6 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  OPLINK [OPLINK Communications Inc.]
Homepage  http://www.oplink.com
Logo 

   
 5 page
background image
46335 Landing Pkwy‧Fremont CA 94538-6407‧Tel: 510-933-7200‧Fax: 510-933-7300‧Email: info@oplink.com‧Web: www.oplink.com
Page 5 of 6
S0489. Rev.01 2015-02-27
TRBUG1CxBx000E2G
Multi-rate Gigabit & Fast Ethernet Transceivers
Bi-Directional SFP 1000BASE 10KM LC Receptacle
Example of SFP host board schematic
Application Notes
Electrical interface: All signal interfaces are compliant with
the SFP MSA specification. The high speed DATA interface
is differential AC-coupled internally with 1
μF and can be
directly connected to a 3.3V SERDES IC. All low speed
control and sense output signals are open collector TTL
compatible and should be pulled up with a 4.7 - 10k
Ω
resistor on the host board.
Loss of Signal (LOS): The Loss of Signal circuit monitors
the level of the incoming optical signal and generates logic
HIGH when an insufficient photocurrent is produced.
TX Fault: The output indicates LOW when the transmitter is
operating normally and HIGH with a laser fault including
laser end-of-life. TX Fault is an open collector/drain output
and should be pulled up with a 4.7 - 10k
Ω resistor on the
host board. TX Fault is non-latching (automatically de-
asserts when fault goes away).
TX Disable: When the TX Disable pin is at logic HIGH, the
transmitter optical output is disabled (less than -45dBm).
Serial Identification: The module definition of SFP is
indicated by the three module definition pins, MOD_DEF(0),
MOD_DEF(1)
and
MOD_DEF(2).
Upon
power
up,
MOD_DEF(1:2) appear as NC (no connection), and
MOD_DEF(0) is TTL LOW. When the host system detects
this condition, it activates the serial protocol (standard two-
wire I2C serial interface) and generates the serial clock
signal (SCL). The negative edge clocks data from the SFP
EEPROM.
The serial data signal (SDA) is for serial data transfer. The
host uses SDA in conjunction with SCL to mark the start
and end of serial protocol activation.
The data transfer protocol and the details of the mandatory
and vendor specific data structures are defined in the SFP
MSA. EEPROM ID is per SFF-8472, Rev. 9.4.
Power supply and grounding: The power supply line
should be well-filtered. All 0.1
μF power supply bypass
capacitors should be as close to the transceiver module as
possible.




Html Pages

1  2  3  4  5  6 


Datasheet Download




Link URL

Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Bookmark   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com 2003 - 2017    


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl