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GS8673EQ18BK-550S Datasheet(PDF) 7 Page - GSI Technology |
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GS8673EQ18BK-550S Datasheet(HTML) 7 Page - GSI Technology |
7 / 25 page GS8673EQ18/36BK-725S/625S/550S Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03 6/2014 7/25 © 2012, GSI Technology Error Correction (ECC) These devices implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on each DDR data word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/Q[26:18], and D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to the user). The ECC algorithm neither corrects nor detects multi-bit errors. However, ECCRAMs are architected in such a way that a single SER event very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit” represents the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-bit errors results in the SER mentioned previously (i.e., <0.002 FITs/Mb (measured at sea level)). Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data storage. Frequently, SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”) for error detection (either simple parity error detection, or system-level ECC error detection and correction). Such error-bit allocation is unnecessary with ECCRAMs; the entire memory array can be utilized for data storage, effectively providing 12.5% greater storage capacity compared to SRAMs of the same density not equipped with on-chip ECC. Input Timing These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various synchronous inputs. Specifically: ↑CK and ↑CK latch all address (SA) inputs. ↑CK latches all control (R, W) inputs. ↑KD[1:0] and ↑KD[1:0] latch particular write data (D) inputs, as follows: • ↑KD0 and ↑KD0 latch D[17:0] in x36, and D[8:0] in x18. • ↑KD1 and ↑KD1 latch D[35:18] in x36, and D[17:9] in x18. Output Timing These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is tightly aligned with read data in order to enable reliable source-synchronous data transmission. Output timing is generated by ↑CK and ↑CK, as follows: • ↑CK generates ↑CQ[1:0], ↓CQ[1:0], Q1 active, and Q2 inactive. • . ↑CK generates ↑CQ[1:0], ↓CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive. Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations. ↑CQ[1:0] and ↑CQ[1:0] align with particular read data (Q) and read data valid (QVLD) outputs, as follows: • ↑CQ0 and ↑CQ0 align with Q[17:0], QVLD0 in x36, and with Q[8:0], QVLD0 in x18. • ↑CQ1 and ↑CQ1 align with Q[35:18], QLVD1 in x36, and with Q[17:9], QVLD1 in x18. |
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