GS8673ED18/36BK-725S/625S/550S

72Mb SigmaQuad-IIIe™

Burst of 4 ECCRAM™

Up to 725 MHz

Rev: 1.04 6/2015

1/25

© 2012, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

260 Pin BGA

Commercial Temp

Industrial Temp

Features

• For use with GSI SRAM Port IP

• 2Mb x 36 and 4Mb x 18 organizations available

• 725 MHz maximum operating frequency

• 725 MT/s peak transaction rate (in millions per second)

• 104 Gb/s peak data bandwidth (in x36 devices)

• Separate I/O DDR Data Buses

• Non-multiplexed SDR Address Bus

• One operation - Read or Write - per clock cycle

• Burst of 4 Read and Write operations

• 3 cycle Read Latency

• On-chip ECC with virtually zero SER

• 1.35V core voltage

• 1.2V or 1.35V or 1.5V I/O interface (HSTL or SSTL)

• Configurable ODT (on-die termination)

• ZQ pin for programmable driver impedance

• ZT pin for programmable ODT impedance

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 260 pin, 14 mm x 22 mm, 1 mm ball pitch BGA package

–K: 5/6 RoHS-compliant package



–GK: 6/6 RoHS-compliant package

SigmaQuad-IIIe™ Family Overview

SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

ECCRAMs. Although very similar to GSI's second generation

of networking SRAMs (the SigmaQuad-II/SigmaDDR-II

family), these third generation devices offer several new

features that help enable significantly higher performance.

Clocking and Addressing Schemes

The GS8673ED18/36BK SigmaQuad-IIIe ECCRAMs are

synchronous devices. They employ three pairs of positive and

negative input clocks; one pair of master clocks, CK and CK,

and two pairs of write data clocks, KD[1:0] and KD[1:0]. All

six input clocks are single-ended; that is, each is received by a

dedicated input buffer.

CK and CK are used to latch address and control inputs, and to

control all output timing. KD[1:0] and KD[1:0] are used solely

to latch data inputs.

Each internal read and write operation in a SigmaQuad-IIIe B4

ECCRAM is four times wider than the device I/O bus. An

input data bus de-multiplexer is used to accumulate incoming

data before it is simultaneously written to the memory array.

An output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-IIIe B4 ECCRAM is always two address

pins less than the advertised index depth (e.g. the 4M x 18 has

1M addressable index).

On-Chip ECC

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by SER events such as cosmic rays, alpha particles,

etc. The resulting Soft Error Rate of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no on-chip ECC,

which typically have an SER of 200 FITs/Mb or more.

All quoted SER values are at sea level in New York City.

Parameter Synopsis

Speed Grade

Max Operating Frequency

Read Latency

-725S

725 MHz

3 cycles

1.3V to 1.4V

-625S

625 MHz

3 cycles

1.3V to 1.4V

-550S

550 MHz

3 cycles

1.3V to 1.4V