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X1240V8I Datasheet(PDF) 9 Page - Xicor Inc. |
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X1240V8I Datasheet(HTML) 9 Page - Xicor Inc. |
9 / 19 page X1240 9 the address counter would point to location 7 on the page that was just written. If the master supplies more than the maximum bytes in a page, then the previously loaded data is over written by the new data, one byte at a time. The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the non-volatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 8 for the address, acknowl- edge, and data transfer sequence. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it’s associated ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be affected. Acknowledge Polling The disabling of the inputs during non-volatile write cycles can be used to take advantage of the typical 5mS write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the device initiates the internal non-volatile write cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the non-volatile write cycle then no ACK will be returned. If the device has com- pleted the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Table 9. READ OPERATIONS There are three basic read operations: Current Address Read, Random Read, and Sequential Read. Current Address Read Internally the device contains an address counter that maintains the address of the last word read incre- mented by one. Therefore, if the last read was to address n, the next read operation would access data from address n+1. On power up, the sixteen bit address is initialized to 0h. In this way, a current address read can be initiated immediately after the power on reset to download the contents of memory starting at the first location. Figure 9. Acknowledge Polling Sequence Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master ter- minates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to Figure 10 for the address, acknowledge, and data transfer sequence. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. ACK returned? Issue Slave Address Byte (Read or Write) Byte load completed by issuing STOP. Enter ACK Polling Issue STOP Issue START NO YES Issue STOP NO Continue normal Read or Write command sequence PROCEED YES nonvolatile write Cycle complete. Continue command sequence? |
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