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X40626S14-4.5A Datasheet(PDF) 1 Page - Xicor Inc. |
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X40626S14-4.5A Datasheet(HTML) 1 Page - Xicor Inc. |
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1 / 23 page  REV 1.1.15 2/11/04 Characteristics subject to change without notice. 1 of 23 www.xicor.com 64K X40626 8K x 8 Bit Dual Voltage CPU Supervisor with 64K Serial EEPROM FEATURES • Dual voltage monitoring —V2Mon operates independent of VCC •Watchdog timer with selectable timeout intervals •Low VCC detection and reset assertion —Four standard reset threshold voltages —User programmable VTRIP threshold —Reset signal valid to VCC=1V •Low power CMOS —20µA max standby current, watchdog on —1µA standby current, watchdog OFF • 64Kbits of EEPROM —64 byte page size • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512 bytes of EEPROM array with programmable Block Lock™ protection • 400kHz 2-wire interface —Slave addressing supports up to 4 devices on the same bus • 2.7V to 5.5V power supply operation •Available Packages —14-lead SOIC —14-lead TSSOP DESCRIPTION The X40626 combines four popular functions, Power-on Reset Control, Watchdog Timer, Dual Supply Voltage Supervision, and Serial EEPROM Memory in one pack- age. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator to stabi- lize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontrol- ler fails to restart a timer within a selectable time-out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET is asserted until VCC returns to proper BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power on and Generation VTRIP + - RESET Reset Low Voltage Status Register Protect Logic 64KB Watchdog Transition Detector WP VCC Threshold Reset logic S0 S1 V2 Monitor Logic + - VTRIP2 V2MON V2FAIL EEPROM Array Preliminary Information |
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