S-93L76A

10



Initial Delivery State

Initial delivery state of all addresses is “FFFFh”.



Operation

All instructions are executed by making CS “H” and then inputting DI at the rising edge of the SK pulse. An instruction

is input in the order of its start bit, instruction, address, and data. The start bit is recognized when “H” of DI is input at

the rising edge of SK after CS has been made “H”. As long as DI remains “L”, therefore, the start bit is not recognized

even if the SK pulse is input after CS has been made “H”. The SK clock input while DI is “L” before the start bit is input

is called a dummy clock. By inserting as many dummy clocks as required before the start bit, the number of clocks the

internal serial interface of the CPU can send out and the number of clocks necessary for operation of the serial memory

IC can be adjusted. Inputting the instruction is complete when CS is made “L”. CS must be made “L” once during the

“L” of CS indicates a standby status. In this status, input of SK and DI is invalid, and no instruction is accepted.

1.

Reading (READ)

The READ instruction is used to read the data at a specified address. When this instruction is executed, the

outputs “L”. Subsequently, 16 bits of data are sequentially output at the rising edge of SK.

If SK is output after the 16-bit data of the specified address has been output, the address is automatically

incremented, and the 16-bit data of the next address is then output. By inputting SK sequentially with CS kept at

CS

1

3 4 5 6

7 8 9 10 11 12 13 14 15 16

2

26 27 28 29 30 31

42 43 44 45 46

32

48

SK

1

1

X

0

DI

High-Z

DO

High-Z

47

Figure 6 Read Timing