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S-8223AAB-I6T1U Datasheet(PDF) 11 Page - Seiko Instruments Inc |
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S-8223AAB-I6T1U Datasheet(HTML) 11 Page - Seiko Instruments Inc |
11 / 30 page BATTERY PROTECTION IC FOR 2-SERIAL / 3-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.0_00 S-8223A/B/C/D Series 11 3. 2 Nch open-drain output product in S-8223A/C Series Set SW4 and SW5 to OFF. 3. 2. 1 Active "H" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1 = 9.4 V, V2 = V3 = 9.3 V, V5 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V5 = 0 V. I2 is the CO pin sink current (ICOL) at that time. 3. 2. 2 Active "L" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1= V2 = V3 = 3.5 V, V5 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 = 5.2 V, V2 = 2.8 V, V3 = 2.5 V, V5 = 0 V. I2 is the CO pin sink current (ICOL) at that time. 3. 3 S-8223B/D Series Set SW4 and SW5 to OFF. 3. 3. 1 CO pin source current (ICOH) Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = VCOH − 0.5 V. I2 is the CO pin source current (ICOH) at that time. 3. 3. 2 CO pin sink current (ICOL) Set SW5 to ON after setting V1 = V2 = V3 = 3.5 V, V5 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 4. Overcharge detection delay time (tCU), overcharge release delay time (tCL) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in Nch open-drain output product of the S-8223A/C Series. Increase V1 up to 5.2 V after setting V0 = 0 V, V1 = V2 = V3 = 3.5 V. The overcharge detection delay time (tCU) is the time period until the CO pin output inverts. After that, decrease V1 down to 3.5 V. The overcharge release delay time (tCL) is the time period until the CO pin output inverts. 5. Overcharge timer reset delay time (tTR) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8223A/C Series and in the S-8223B/D Series, and set SW1 to ON in Nch open-drain output product of the S-8223A/C Series. Increase V1 up to 5.2 V (first rise), and decrease V1 down to 3.5 V within the overcharge detection delay time (tCU) after setting V0 = 0 V, V1 = V2 = V3 = 3.5 V. After that, increase V1 up to 5.2 V again (second rise), and detect the time period until the CO pin output inverts. When the period from when V1 has fallen to the second rise is short, CO pin output inverts after tCU has elapsed since the first rise. If the period is gradually made longer, CO pin output inverts after tCU has elapsed since the second rise. The overcharge timer reset delay time (tTR) is the period from V1 fall until the second rise at that time. |
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