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S-8224AAU-I8T1U Datasheet(PDF) 8 Page - Seiko Instruments Inc |
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S-8224AAU-I8T1U Datasheet(HTML) 8 Page - Seiko Instruments Inc |
8 / 33 page BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) S-8224A/B Series Rev.1.2_00 8 Absolute Maximum Ratings Table 5 (Ta = +25°C unless otherwise specified) Item Symbol Applied Pin Absolute Maximum Rating Unit Input voltage between VDD pin and VSS pin VDS VDD VSS − 0.3 to VSS + 28 V Input pin voltage VIN VC1 VSS − 0.3 to VSS + 28 V VC2, VC3, VC4 VDD − 28 to VDD + 0.3 V CTL VSS − 0.3 to VDD + 0.3 V CO pin output voltage S-8224A Series CMOS output VCO CO VSS − 0.3 to VDD + 0.3 V Nch open-drain output VSS − 0.3 to VSS + 28 V S-8224B Series VSS − 0.3 to VDD + 0.3 V Operation ambient temperature Topr − −40 to +85 °C Storage temperature Tstg − −40 to +125 °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Thermal Resistance Value Table 6 Item Symbol Condition Min. Typ. Max. Unit Junction-to-ambient thermal resistance *1 θja SNT-8A Board A − 211 − °C/W Board B − 173 − °C/W Board C − − − °C/W Board D − − − °C/W Board E − − − °C/W *1. Test environment: compliance with JEDEC STANDARD JESD51-2A Remark Refer to " Power Dissipation" and "Test Board" for details. |
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