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S-1200B26-M5T1U Datasheet(PDF) 11 Page - Seiko Instruments Inc |
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S-1200B26-M5T1U Datasheet(HTML) 11 Page - Seiko Instruments Inc |
11 / 37 page HIGH RIPPLE-REJECTION LOW DROPOUT LOW INPUT-AND-OUTPUT CAPACITANCE CMOS VOLTAGE REGULATOR Rev.5.1_01 S-1200 Series 11 Standard Circuit ON/OFF VSS VOUT VIN CIN *1 CL *2 Input Output GND Single GND *1. CIN is a capacitor for stabilizing the input. *2. A ceramic capacitor of 0.1 μF or more can be used for CL. Figure 11 Caution The above connection diagram and constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. Condition of Application Input capacitor (CIN): 0.1 μF or more Output capacitor (CL): 0.1 μF or more ESR of output capacitor: 1.0 Ω or less Caution Generally a series regulator may cause oscillation, depending on the selection of external parts. Check that no oscillation occurs with the application using the above capacitor. Selection of Input and Output Capacitors (CIN, CL) The S-1200 Series requires an output capacitor between the VOUT pin and the VSS pin for phase compensation. Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1 μF or more in the entire temperature range. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be 0.1 μF or more, and the ESR must be 1.0 Ω or less. The value of the output overshoot or undershoot transient response varies depending on the value of the output capacitor. The required capacitance of the input capacitor differs depending on the application. The recommended value for an application is CIN ≥ 0.1 μF, CL ≥ 0.1 μF; however, when selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature characteristics, on the actual device. |
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