NB7L216MNEVB datasheet(5/11 Pages) ONSEMI

Part #	NB7L216MNEVB

Description	2.5 V / 3.3 V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination

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NB7L216

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5

Table 5. AC CHARACTERISTICS (VCC = 2.375 V to 3.465 V, VEE = 0 V; (Note 1))

Symbol

Characteristic

−40°C

25°C

85°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

VOUTPP Output Voltage Amplitude (@ VINPPmin)

fin ≤ 7.0 GHz

fin ≤ 8.5 Ghz (See Figure 4)

275

100

380

250

275

100

380

250

275

100

380

250

mV

fDATA

Maximum Operating Data Rate

10

12

10

12

10

12

Gb/s

|S21|

Power Gain DC to 7 GHz

35

dB

|S11|

Input Return Loss @ 7 GHz

−10

dB

|S22|

Output Return Loss @ 7 GHz

−5

dB

|S12|

Reverse Isolation (Differential Configuration)

−25

dB

IIP3

Input Third Order Intercept

0

dBm

tPLH,

tPHL

Propagation Delay to Output Differential @ 1 GHz

60

120

180

60

120

180

60

120

180

ps

tSKEW

Duty Cycle Skew (Note 1)

Device to Device Skew (Note 6)

2

5

10

20

2

5

10

20

2

5

10

20

ps

tJITTER

RMS Random Clock Jitter

fin v 8.5 Ghz (Note 4)

Peak-to-Peak Data Dependent Jitter (Note 5)

fDATA = 3.5 Gb/s

fDATA = 5.0 Gb/s

fDATA = 10 Gb/s

fDATA = 12 Gb/s

0.1

1

3

4

0.5

7

9

0.1

1

3

4

0.5

7

9

0.1

1

3

4

0.5

7

9

ps

VINPP

Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 3 and Figure 12)

20

2500

20

2500

20

2500

mV

tr

tf

Output Rise/Fall Times @ 0.5 Ghz (20% − 80%)

Q, Q

30

45

30

45

30

45

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating

temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values

are applied individually under normal operating conditions and not valid simultaneously.

1. Measured by forcing VINPPmin from a 50% duty cycle clock source. All loading with an external RL = 50 W to VTT =VCC − 2.0 V. Input edge

rates 40 ps (20%− 80%).

2. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.

3. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single-ended measurement operating in differential mode.

4. Additive RMS jitter with 50% duty cycle clock signal.

5. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 223−1.

6. Device to device skew is measured between outputs under identical transition @ 1 GHz.

0

50

100

150

200

250

300

350

400

450

500

246789

10

11

12

0

Figure 4. Output Voltage Amplitude (VOUTPP) versus

Input Clock Frequency (fIN) and Temperature

(VINPP = 400 mV, VCC = 3.3 V and VEE = 0 V)

25°C

−40°C

85°C

INPUT CLOCK FREQUENCY (GHz)

0

50

100

150

200

250

300

350

400

450

500

24

6

789

10

11

12

0

−40°C

25°C

85°C

INPUT CLOCK FREQUENCY (GHz)

Figure 5. Output Voltage Amplitude (VOUTPP) versus

Input Clock Frequency (fIN) and Temperature

(VINPP = 20 mV, VCC = 3.3 V and VEE = 0 V)

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