HY62K(U,V)T08081E Series

Rev 02 / Apr. 2001

8

Notes(WRITE CYCLE):

1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition

among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high

or /WE going high.

5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,

input of opposite phase of the output must not be applied because bus contention can occur.

6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high

impedance state.

DATA RETENTION CHARACTERISTIC

°C to 70°C (Normal)/-25°C to 85°C (Extended) /-40°C to 85°C (Industrial),

unless otherwise specified.

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Vcc for Data Retention

CS>Vcc-0.2V,

2.0

-

3.6

V

Data Retention Current

Vcc=3.0V,

/CS>Vcc - 0.2V,

0~70

°C

-

0.5

5

uA

-25~85

°C or

-40~85

°C

-

0.5

8

uA

tCDR

Chip Deselect to Data

Retention Time

See Data Retention

0

-

-

ns

tR

Operating Recovery Time

Timing Diagram

-

-

ns

Notes

°C.

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM

CS

VDR

CS>VCC-0.2V

tCDR

tR

VSS

VCC

2.7V/3.0V

2.2V

DATA RETENTION MODE