Digital Potentiometers

4

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Note 1:

Note 2:

wiper terminal is unloaded and measured with a high-input-impedance voltmeter.

Note 3:

The DNL and INL are measured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ =

the wiper is driven with 200µA (MAX5477), 40µA (MAX5478), or 20µA (MAX5479).

Note 4:

The wiper resistance is measured using the source currents given in Note 3.

Note 5:

The devices draw current in excess of the specified supply current when the digital inputs are driven with voltages between

Note 6:

Wiper at midscale with a 10pF load (DC measurement). L_ = GND, an AC source is applied to H_, and the W_ output is

measured. A 3dB bandwidth occurs when the AC W_/H_ value is 3dB lower than the DC W_/H_ value.

Note 7:

The programming current exists only during power-up and EEPROM writes.

Note 8:

Note 9:

Digital timing is guaranteed by design and characterization, and is not production tested.

Note 10: This is measured from the STOP pulse to the time it takes the output to reach 50% of the output step size (divider mode). It

is measured with a maximum external capacitive load of 10pF.

Note 11: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the I

tion document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf

Note 12: The idle time begins from the initiation of the STOP pulse.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCL High Time

0.6

µs

SCL Low Time

1.3

µs

Data Setup Time

100

ns

Data Hold Time

0

0.9

µs

SDA, SCL Rise Time

300

ns

SDA, SCL Fall Time

300

ns

Setup Time for STOP Condition

0.6

µs

Bus Free Time Between STOP

and START Condition

Minimum power-up rate = 0.2V/µs

1.3

µs

Pulse Width of Spike Suppressed

50

ns

Capacitive Load for Each Bus

Line

(Note 11)

400

pF

Write NV Register Busy Time

(Note 12)

12

ms

TIMING CHARACTERISTICS (continued)