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RT5509 Datasheet(PDF) 14 Page - Richtek Technology Corporation |
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RT5509 Datasheet(HTML) 14 Page - Richtek Technology Corporation |
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14 / 58 page  RT5509 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5509-00 August 2017 14 Operation Mode The RT5509 can operate in six different modes which are power-down / suspend / operating / mute / off / fault. Internal functional block operational status in different mode is depicted in Figure 5. : Normal operation : Operational with zero input : Power down : Output floating PLL I 2 C I 2 S AMP SPK PWDN OP MUTE OFF FAULT Mode Blk SUSP Figure 5. Operation Mode Power-Down Mode (PWDN = 1) When PWDN is set to 1, chip will enter power-down mode. In power-down mode, power consumption is minimum and PWM outputs are floating. I2C remains awake in power-down mode. If PWDN is set to 1, I2S is also disabled. Suspend Mode (BCK/LRCK Invalid) When BCK/LRCK is invalid, chip will enter suspend mode. In suspend mode, most of the data path are off, and PWM outputs are floating. I2C remains awake in power-down mode. PLL keeps awake used to monitor BCK/LRCK on I2S bus to see if they are correct. Operating Mode (PWDN = 0, SPKE = 1, SPKM = 0, AMPE = 1) Operating mode is selected via PWDN/SPKE/ SPKM/AMPE at register 0xXX. One of I2S interface (DATA1/DATA2) is selected as the audio source. In operating mode, the frequency of LRCK should be the same as I2SFS. Mute Mode (PWDN = 0, SPKE = 1, SPKM = 1, AMPE = 1) Soft muting is used to prevent pop noise and is implemented in the speaker protection block when SPKE set to logic 1. Ramp up/down in exponential scale are implemented when switching between muted and unmuted mode. Off Mode (PWDN = 0, SPKE = 1, AMPE = 0) The outputs of class-D are floating and chip is biased in off mode. Soft mute can be executed if AMPDS at register 0xXX equals to 1 before chip enters off mode. Fault Mode Chip enters fault mode when an error event of physical protection mechanisms occurs (OCP/OVP/UVP/OTP). The outputs of class-D are floating in Fault mode. The system exits from Fault mode after the protection event released for a checking cycle of about 200ms. |
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