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TLC5620CD Datasheet(PDF) 3 Page - Texas Instruments |
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TLC5620CD Datasheet(HTML) 3 Page - Texas Instruments |
3 / 10 page TLC5620C, TLC5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description The TLC5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to the reference source. Each DAC output is buffered by a configurable-gain output amplifier that can be programmed to times 1 or times 2 gain. On power up, the DACs are reset to CODE 0. Each output voltage is given by: V O (DACA|B|C|D) + REF CODE 256 (1 ) RNG bit value) where CODE is in the range 0 to 255 and the range (RNG) bit is 0 or 1 within the serial control word. Table 1. Ideal Output Transfer D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE 0 0 0 0 0 0 0 0 GND 0 0000001 (1/256) × REF (1+RNG) • ••••••• • • ••••••• • 0 1111111 (127/256) × REF (1+RNG) 1 0000000 (128/256) × REF (1+RNG) • ••••••• • • ••••••• • 1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG) data interface With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit (MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4. RNG A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DAC Update CLK DATA LOAD tsu(DATA-CLK) tv(DATA-CLK) tsu(CLK-LOAD) tw(LOAD) tsu(LOAD-CLK) Figure 1. LOAD-Controlled Update (LDAC = Low) |
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