Pin

Name

Description

15

PWIDTH

A ±5% resistor value is recommended. When this pin is connected to Vcc througha1M resistor, the RF amplifi-

ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier

ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance

between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation

with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the

sleep mode.

16

VCC2

VCC2 is the positive supply voltage pin for the receiver RF section and transmitter oscillator. Pin 16 must be by-

passed with an RF capacitor, and must also be bypassed witha1to10µF tantalum or electrolytic capacitor. See

the ASH Transceiver Designer’s Guide for additional information.

17

CNTRL1

CNTRL1 and CNTRL0 select the receive and transmit modes. CNTRL1 and CNTRL0 both high place the unit in

the receive mode. CNTRL1 high and CNTRL0 low place the unit in the ASK transmit mode (TR3100). CNTRL1

low and CNTRL0 high place the unit in the OOK transmit mode. CNTRL1 and CNTRL0 both low place the unit in

the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to

300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An

input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum

source current of 40 µA. A logic low requires a maximum sink current of 25 µA (1 µA in sleep mode). This pin

must be held at a logic level; it cannot be left unconnected.

18

CNTRL0

CNTRL0 is used with CNTRL1 to control the receive and transmit modes of the transceiver. CNTRL0 is a

high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input

voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV

should not be applied to this pin. A logic high requires a maximum source current of 40 µA. A logic low requires a

maximum sink current of 25 µA (1 µA in sleep mode). This pin must be held at a logic level; it cannot be left un-

connected.

19

GND3

GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

20

RFIO

RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting

an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series match-

ing coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three

components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to

ground is required for ESD protection.

11

S M - 2 0H P C B P ad L ayou t

D i m e ns i o ns i n i n c hes .

.0 9

.3 7 0

0. 000

.0 6 5

.1 0 5

.1 4 5

.1 8 5

.2 2 5

.2 6 5

.3 0 5

.3 4 5

.4 3 5