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GS8672Q20BGE-400 Datasheet(PDF) 5 Page - GSI Technology |
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GS8672Q20BGE-400 Datasheet(HTML) 5 Page - GSI Technology |
5 / 28 page GS8672Q20/38BE-500/450/400 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01c 8/2017 5/28 © 2011, GSI Technology Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O ECCRAMs can cut the RAM’s bandwidth in half. SigmaQuad-II+ B2 ECCRAM DDR Read The read port samples the status of the Address Input and R pins at each rising edge of K. A Low on the Read Enable pin, R, begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied High), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied High). Clocking in a High on the Read Enable pin, R, begins a read port deselect cycle. SigmaQuad-II+ B2 ECCRAM DDR Write The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A Low on the Write Enable pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write address. Clocking in a High on W causes a write port deselect cycle. |
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