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BQ25600CYFFT Datasheet(PDF) 5 Page - Texas Instruments |
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BQ25600CYFFT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 51 page  5 bq25600C www.ti.com SLUSD36 – SEPTEMBER 2017 Product Folder Links: bq25600C Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. SCL F5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. SDA E4 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor. STAT E5 DO Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-k Ω resistor. The STAT pin indicates charger status. Charge in progress: LOW Charge complete or charger in SLEEP mode: HIGH Charge suspend (fault response): Blink at 1Hz SW A2 P Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor from SW to BTST. B2 SYS C2 P Converter output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 20 µF closely to the SYS pin. D2 E2 F2 Thermal Pad — P Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. NC D3, D4 AI No Connect. Leave this pin floating. VAC A5 AI Input voltage sensing. This pin must be connected to VBUS. VBUS A4 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it as close as possible to IC. B4 |
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