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CS61577 Datasheet(PDF) 35 Page - Cirrus Logic |
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CS61577 Datasheet(HTML) 35 Page - Cirrus Logic |
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35 / 44 page  The evaluation board supports 100 Ω twisted-pair T1, 75 Ω coax E1, and 120Ω twisted-pair E1 op- eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The CD B61 5 3 5 A , CD B61 58A, CDB61574A, CDB61575, CDB61304A, and CDB61305A are supplied with a 1:1.15 transmit transformer in- stalled for T1 applications. An additional 1:1:1.26 transformer for E1 applications is provided with the board. This transformer requires JP5 to be jumpered across F-F for 75 Ω coax E1 applica- tions. T he CDB6 15 34 , CDB6 15 35 , CDB6158, CDB61574, and CDB61577 require the JP8 jumper to be out for 75 Ω coax E1 applications. This inserts resistor R2 to reduce the transmit pulse amplitude and meet the 2.37 V nominal pulse amplitude requirement in CCITT G.703. In addition, R2 increases the equivalent load imped- ance across TTIP and TRING. RECEIVE CIRCUIT The receive line interface signal is input at the RTIP and RRING binding posts. The receive sig- nal is transformer coupled to the line interface de- vice through a center-tapped 1:2 transformer. The transformer produces ground referenced pulses of equal amplitude and opposite polarity on RTIP and RRING. The receive line interface is terminated by resis- tors R9 and R10. The evaluation boards are sup- plied from the factory with 200 Ω resistors for ter- minating 100 Ω T1 twisted-pair lines. Resistors R9 and R10 should be replaced with 240 Ω resis- tors for terminating 120 Ω E1 twisted-pair lines or 150 Ω resistors for terminating 75Ω E1 coaxial lines. Two 243 Ω resistors and two 150Ω resistors are included with the evaluation board for this purpose. The recovered clock and data signals are avail- able o n BN C ou tpu t s lab eled RCLK, RPOS(RDATA), and RNEG(BPV). In the Hard- ware and Host operating modes, data is output on the RPOS(RDATA) and RNEG(BPV) connectors in dual NRZ format. In the Extended Hardware operating mode, data is output in NRZ format on the RPOS(RDATA) connector and bipolar viola- tions are reported on the RNEG(BPV) connector. QUARTZ CRYSTAL A quartz crystal must be installed in socket Y1 for all devices except the CS6158 and CS6158A. A Crystal Semiconductor CXT6176 crystal is rec- ommended for T1 operation and a CXT8192 is recommended for E1 operation. The evaluation board has a CXT6176 installed at the factory and a CXT8192 is also provided with the board. The CDB6158 and CDB6158A have resistor R13 installed instead of a crystal. This connects the RT pin of the device to the +5 Volt supply. ALTERNATE CLOCK INPUT The ACLKI BNC input provides the alternate clock reference for the line interface device (ACLK for the CS61534) when JP4 is jumpered across C-C. This clock is required for the CS61534, CS61535, CS6158, and CS6158A op- eration but is optional for all other line interface devices. If ACLKI is provided, it may be desir- able to connect both C-C and D-D positions on JP4 to terminate the external clock source provid- ing ACLKI with the 51 Ω resistor R1. If ACLKI is optional and not used, connector JP4 should be jumpered across D-D to ground pin 1 of the de- vice through resistor R1. TRANSFORMER SELECTION To permit the evaluation of other transformers, Table 2 lists the transformer and line interface de- vice combinations that can be used in T1 and E1 LINE INTERFACE EVALUATION BOARD DS40DB3 35 |
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Similar Description - CS61577 |
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