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CS61577 Datasheet(PDF) 4 Page - Cirrus Logic

Part No. CS61577
Description  T1/E1 LINE INTERFACE
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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ANALOG SPECIFICATIONS (TA = -40
°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Receiver
RTIP/RRING Input Impedance
-
50k
-
Sensitivity Below DSX (0dB = 2.4V)
-13.6
500
-
-
-
-
dB
mV
Loss of Signal Threshold
-
0.30
-
V
Data Decision Threshold
T1, DSX-1
(Note 20)
T1, DSX-1
(Note 21)
T1, (FCC Part 68) and E1 (Note 22)
60
53
45
65
65
50
70
77
55
% of peak
% of peak
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
(Note 23)
10kHz - 100kHz
2kHz
10Hz and below
0.4
6.0
300
-
-
-
-
-
-
UI
UI
UI
Jitter Attenuator
Jitter Attenuation Curve Corner Frequency
(Notes 17, 24)
-
6
-
Hz
Attenuation at 10kHz Jitter Frequency
(Notes 17, 24)
-
50
-
dB
Attenuator Input Jitter Tolerance (Before Onset
of FIFO Overflow or Underflow Protection)
(Notes 17, 24)
12
23
-
UI
Notes: 20. For input amplitude of 1.2 Vpk to 4.14 Vpk.
21. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
22. For input amplitude of 1.05 Vpk to 3.3 Vpk.
23. Jitter tolerance increases at lower frequencies. See Figure 11.
24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
CS61577
4
DS155PP2




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