EC24C02B

2Kbit I

Page 6 of 17

5F12N-Rev. F002

3.2Start Data Transfer(B)

A high-to-low transition of the SDA line while the clock( SCL) is high determines a Start condition.

All commands must be preceded by a Start condition.

3.3 Stop Data Transfer(C)

A low-to-high transition of the SDA line while the clock(SCL) is high determines a Stop condition.

All operations must be ended with a Stop condition.

3.4

Data Valid(D)

The state of the data line represents valid data when, after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low period of the clock signal. There is one clock Pulse

per bit of data.

Each data transfer is initiated with a Start condition and terminated with a Stop condition.

The number of data bytes transferred between Start and Stop conditions is determined by the master

device and is, theoretically, unlimited (although only the last sixteen will be stored when doing a

write operation). When an overwrite does occur, it will replace data in a first-in first-out (FIFO) fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception

ofeach byte.The master device must generate an extra clock pulse which is associated with this Acknowledge

bit.

Note: The EC24C02B does not generate any Acknowledge bits

if

an

internal

programming

cycle

is

in progress.

The device that acknowledges has to pull down the SDA line during the acknowledage clock pulse in such a way

that the SDA line is stable low during the high period of the acknowledge related clock pulse.

Of course, setup and hold times must be taken into account. During reads, a master must signal an end

of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave.

In this case, the slave (EC24C02B) will leave the data line high to enable the master to generate the Stop

condition.