EC24C32A/64A

32K/64K-bit 2-WIRE SERIAL CMOS EEPROM

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5F18N-Rev.F003

The data word address lower five (32K/64K) bits are internally incremented following the receipt of each data word.

The higher data word address bits are not incremented, retaining the memory page row location. When the word

address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same

page. If more than 32 (32K/64K) data and previous data will be overwritten. words are

transmitted to the

EEPROM, the data word address will "roll over" and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are

disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device

address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has

completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.

Figure 4: Device Address

Figure 5: Byte Write

Figure 6: Page Write