EC24C02B

2Kbit I

Page 11 of 17

5F12N-Rev. F002

7.3 Sequential Read

Sequential reads are initiated in the same way as a random read, except that once the EC24C02B transmits

the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read.

This directs the EC24C02B to transmit the next sequentially-addressed 8-bit word (Figure 7-3).

To provide sequential reads, the EC24C02B contains an internal Address Pointer that is incremented by one upon

completion of each operation. This Address Pointer allows the entire memory contents to be serially read

during one operation.

7.4 Noise Protection

The EC24C02B employs a Vcc threshold detector circuit which disables the internal erase/write logic if the Vcc is

below 1.5V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper

device operation, even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

FIGURE 7-2 RANDOM READ

FIGURE 7-3:SEQUENTIAL READ