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EC24CXXANF2GX Datasheet(PDF) 6 Page - E-CMOS Corporation |
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EC24CXXANF2GX Datasheet(HTML) 6 Page - E-CMOS Corporation |
6 / 18 page EC24C02A/04A/08A/16A 2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM E-CMOS Corp. (www.ecmos.com.tw) Page 6 of 18 5H06N-Rev.F004 Figure 3: Output Acknowledge Device Addressing The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The 4K EEPROM uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. The A0 (P0) pin is no connection. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 (P1) and A0 (P0) pins are no connections. The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0 (P0), A1 (P1) and A2 (P2) pins are no connections. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. DATA SECURITY: The EC24C02A/04A/08A/16A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled |
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