EC24C512B

512K bitsTwo-wire Serial EEPROM

Page 4 of 13

4I09N-Rev.F001

Device Operation

The

EC24C512B

serial

interface

supports

communications using industrial standard 2-wire bus

protocol, such as I

2-WIRE Bus

The two-wire bus is defined as Serial Data (SDA), and

Serial Clock (SCL). The protocol defines any device that

sends data onto the SDA bus as a transmitter, and the

receiving devices as receivers. The bus is controlled by

Master device that generates the SCL, controls the bus

access, and generates the Start and Stop conditions.

The EC24C512B is the Slave device.

The Bus Protocol

Data transfer may be initiated only when the bus is not

busy. During a data transfer, the SDA line must remain

stable whenever the SCL line is high. Any changes in the

SDA line while the SCL line is high will be interpreted as

a Start or Stop condition.

The state of the SDA line represents valid data after a

Start condition. The SDA line must be stable for the

duration of the High period of the clock signal. The data

on the SDA line may be changed during the Low period

of the clock signal. There is one clock pulse per bit of

data. Each data transfer is initiated with a Start condition

and terminated by a Stop condition.

Start Condition

The Start condition precedes all commands to the device

and is defined as a High to Low transition of SDA when

SCL is High. The EEPROM monitors the SDA and SCL

lines and will not respond until the Start condition is met.

Stop Condition

The Stop condition is defined as a Low to High transition

of SDA when SCL is High. All operations must end with

a Stop condition.

Acknowledge

After a successful data transfer, each receiving device is

required to generate an ACK. The Acknowledging device

pulls down the SDA line.

Reset

The EC24C512B contains a reset function in case the 2-

wire bus transmission on is accidentally interrupted (e.g.

a power loss), or needs to be terminated mid-stream.

The reset is initiated when the Master device creates a

Start condition. To do this, it may be necessary for the

Master device to monitor the SDA line while cycling the

SCL up to nine times.(For each clock signal transition to

High, the Master checks for a High level on SDA.)

Standby Mode

While in standby mode, the power consumption is

minimal. The EC24C512B enters into standby mode

during one of the following conditions: a) After Power-up,

while no Op-code is sent; b) After the completion of an

operation and followed by the Stop signal, provided that

the previous operation is not Write related; or c) After the

completion of any internal write operations.

Device Addressing

The Master begins a transmission on by sending a Start

condition, then sends the address of the particular Slave

devices to be communicated. The Slave device address

is 8 bits format as shown in Figure. 5.

The four most significant bits of the Slave address are

fixed (1010) for EC24C512B. The next three bits, A0, A1

and A2, of the Slave address are specifically related to

EEPROM. Up to eight EC24C512B units can be

connected to the 2-wire bus. The last bit of the Slave

address specifies whether a Read or Write operation is to

be performed. When this bit is set to 1, Read operation is

selected. While it is set to 0, Write operation is selected.

After the Master transmits the Start condition and Slave

address byte appropriately, the associated 2-wire Slave

device,EC24C512B, will respond with ACK on the SDA

line.Then EC24C512B will pull down the SDA on the

ninth clock cycle, signaling that it received the eight bits

of data. The EC24C512B then prepares for a Read or

Write operation by monitoring the bus.