EC24C1024AM1GR datasheet(6/14 Pages) E-CMOS

6 / 14 page

EC24C1024A

1024K bits Two-wire Serial EEPROM

E-CMOS Corp. (www.ecmos.com.tw)

Page 6 of 14

5B13N-Rev.F001

Figure 1. Typical System Bus Configuration

Figure 2. output Acknowledge

Figure 3. Start and Stop Conditions

Sequential Read

Sequential Reads can be initiated as either a Current

Address Read or Random Address Read. After the

EC24C1024A sends the initial byte sequence,

the Master device now responds with an ACK indicating

it requires additional data from the EC24C1024A. The

EEPROM continues to output data for each ACK

received. The Master device terminates the sequential

Read operation by pulling SDA High (no ACK) indicating

the last data word to be read,

Diagrams

followed by a Stop condition. The data output is

sequential, with the data from address n followed by the

data from address n+1,n+2 ... etc. The address counter

increments by one automatically, allowing the entire

memory contents to be serially read during sequential

Read operation. When the memory address boundary of

the array is reached, the

address counter “rolls over” to

address 0, and the device continues to output data.

(Refer to Figure 10. Sequential Read Diagram).

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