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5F09N-Rev.F001

EC25C32

32Kbits SPI Serial EEPROM

Device Operation

Status Register

The Status Register accessible by the user consists of 8-bits data for write protection control and write status.

It Hardware Write Protection is enabled or WEN is set to 0. If neither is true, it can be modified by a valid

instruction.

Table 1: Status Register

Note: During internal write cycles, bits 0 to 7 are temporarily 1's.

Table 2: Block Protection by BP0 and BP1

Bit

Symbol

Name

Description

0

RDY

Ready

1

WEN

Write Enable

This represents the write protection status of the device.

When WEN = 0, Status Register and entire array cannot be modified, regardless

Write Enable command (WREN) can be used to set WEN to 1.

Upon power-up stage, WEN is reset to 0.

2

BP0

Block Protect Bit

combinations of the four blocks being protected (Table2).

They are non-volatile memory and programmed to 0 by factory.

3

BP1

Block Protect Bit

4

X

Don’t Care

write operation.

5

X

Don’t Care

6

X

Don’t Care

7

WPEN

Write Protect Enable

This bit can be utilized to enable Hardware Write Protection, together with

WP

pin. If enabled, Status Register becomes read-only. However, the memory

array is not protected by this mode. Hardware Write Protection requires the

write protection)

Level

Status Register Bits

Array Addresses Protected

BP1

BP0

0

0

0

None

1 (1/4)

0

1

0C00h-0FFFh

2 (1/2)

1

0

0800h-0FFFh

3 (All)

1

1

0000h-0FFFh