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5B11N-Rev.F001

EC25C64

64Kbits SPI Serial EEPROM

Op-Code Instructions

The operations of the EC25C64 are controlled by a set of instruction Op-Codes (Table3) that are clocked-in

serially via SI pin. To initiate an instruction, the chip select(CS) must be Low. Subsequently, each Low-to-High

transition of the clock (SCK) will latch a stable level from SI. After the 8-bit Op-Code, it may continue to latch-in

an address and/or data output, data are latched out at the falling edge of SCK. All communications start with

MSB first. Upon the transmission of the last bit but prior to any following Low-to-High transition on SCK, CS

must be brought to High in order to end the transaction and start the operation. The device will enter into

Standby Mode after the operation is completed. data from SI accordingly, or to output data from SO. During

data output, data are latched out at the falling edge of SCK. All communications start with MSB first. Upon

the transmission of the last bit but prior to any following Low-to-High transition on SCK, CS must be brought

to High in order to end the transaction and start the operation. The device will enter into Standby Mode after the

operation is completed.

Notes:

[1] X =

Don’t care bit. However, it is recommended to be “0”.

[2]Some address bits may be don’t care (Table 5).

[3] It is strongly recommended that an appropriate format of Op-Code must be entered. Otherwise, it maycause

unexpected phenomenon to be occurred. Nevertheless, it is illegal to input invalid any Op-Code.

Write Enable

When VCC is initially applied ,the device powers up with both status register and entire array in a write-

disabled state. Upon completion of Write Disable(WRDI),Write Status Register(WRSR) or Write Data to Array

(WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a Write

Enable (WREN) instruction is necessary to set WEN to 1 (Figure.2).

Write Disable

The device can be completely protected from modification by resetting WEN to 0 through the Write Disable

(WRDI) instruction (Figure.3).

Read Status Register

The Read Status(RDSR) instruction reviews the status of Write Protect Enable, Block Protection setting

(Table 2), Write Enable state and RDY status. RDSR is the only instruction

accepted

when

a

write

cycle is under way. It is recommended that the status of Write Enable and RDY be checked, especially prior

to an attempted modification of data. These 8 bits information can be repeatedly output on SO after the initial

Op-Code (Figure.4)

.

Name

Op-Code

Operation

Address

WREN

0000 X110

Set Write Enable Latch

-

-

-

WRDI

0000 X100

Reset Write Enable Latch

-

-

-

RDSR

0000 X101

Read Status Register

-

-

WRSR

0000 X001

Write Status Register

-

-

READ

0000 X011

Read Data from Array

-

WRITE

0000 X010

Write Data to Array

-