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TLV62568DRL Datasheet(PDF) 4 Page - Texas Instruments |
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TLV62568DRL Datasheet(HTML) 4 Page - Texas Instruments |
4 / 26 page 4 TLV62568, TLV62568P SLVSD89A – NOVEMBER 2016 – REVISED APRIL 2017 www.ti.com Product Folder Links: TLV62568 TLV62568P Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V (1) Refer to the Application and Implementation section for further information. 6.3 Recommended Operating Conditions (1) MIN TYP MAX UNIT VIN Input voltage 2.5 5.5 V VOUT Output voltage 0.6 VIN V IOUT Output current 1 A TJ Operating junction temperature –40 125 °C ISINK_PG Sink current at PG pin 1 mA (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.4 Thermal Information THERMAL METRIC(1) TLV62568 TLV62568x UNIT DBV (5 Pins) DRL (6 pins) RθJA Junction-to-ambient thermal resistance 191.6 149.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 141.4 45.7 °C/W RθJB Junction-to-board thermal resistance 44.5 31.1 °C/W ψJT Junction-to-top characterization parameter 34.5 1.3 °C/W ψJB Junction-to-board characterization parameter 43.9 31.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W |
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