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IDT82V2108 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT82V2108 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 272 page  5 INDUSTRIAL TEMPERATURE RANGES IDT82V2108 T1 / E1 / J1 OCTAL FRAMER 3.11.2 T1 / J1 Mode ................................................................................................................................................................................ 47 3.11.2.1 Receive Clock Slave Mode .................................................................................................................................................... 47 3.11.2.1.1 Receive Clock Slave RSCK Reference Mode ........................................................................................................ 48 3.11.2.1.2 Receive Clock Slave External Signaling Mode ...................................................................................................... 50 3.11.2.2 Receive Clock Master Mode ................................................................................................................................................... 50 3.11.2.2.1 Receive Clock Master Full T1/J1 Mode ................................................................................................................. 52 3.11.2.2.2 Receive Clock Master Fractional T1/J1 Mode ....................................................................................................... 52 3.11.2.3 Receive Multiplexed Mode ..................................................................................................................................................... 52 3.11.2.4 Parity Check .......................................................................................................................................................................... 53 3.11.2.5 Offset .................................................................................................................................................................................... 55 3.11.2.6 Output On RSDn/MRSD & RSSIGn/MRSSIG ......................................................................................................................... 55 3.12 PRBS GENERATOR / DETECTOR (PRGD) .......................................................................................................................................... 56 3.12.1 E1 Mode ....................................................................................................................................................................................... 56 3.12.2 T1 / J1 Mode ................................................................................................................................................................................ 57 3.13 TRANSMIT SYSTEM INTERFACE (TRSI) ............................................................................................................................................. 57 3.13.1 E1 Mode ....................................................................................................................................................................................... 57 3.13.1.1 Transmit Clock Slave Mode ................................................................................................................................................... 58 3.13.1.1.1 Transmit Clock Slave TSFS Enable Mode ........................................................................................................... 58 3.13.1.1.2 Transmit Clock Slave External Signaling Mode ................................................................................................... 60 3.13.1.2 Transmit Clock Master Mode .................................................................................................................................................. 61 3.13.1.3 Transmit Multiplexed Mode .................................................................................................................................................... 61 3.13.1.4 Parity Check .......................................................................................................................................................................... 63 3.13.1.5 Offset .................................................................................................................................................................................... 65 3.13.2 T1 / J1 Mode ................................................................................................................................................................................ 68 3.13.2.1 Transmit Clock Slave Mode ................................................................................................................................................... 68 3.13.2.1.1 Transmit Clock Slave TSFS Enable Mode ........................................................................................................... 69 3.13.2.1.2 Transmit Clock Slave External Signaling Mode ................................................................................................... 71 3.13.2.2 Transmit Clock Master Mode .................................................................................................................................................. 72 3.13.2.3 Transmit Multiplexed Mode .................................................................................................................................................... 72 3.13.2.4 Parity Check .......................................................................................................................................................................... 75 3.13.2.5 Offset .................................................................................................................................................................................... 75 3.14 TRANSMIT PAYLOAD CONTROL (TPLC) ............................................................................................................................................ 76 3.14.1 E1 Mode ....................................................................................................................................................................................... 76 3.14.2 T1 / J1 Mode ................................................................................................................................................................................ 76 3.15 FRAME GENERATOR (FRMG) ............................................................................................................................................................. 77 3.15.1 E1 Mode ....................................................................................................................................................................................... 77 3.15.2 T1 / J1 Mode ................................................................................................................................................................................ 78 3.16 HDLC TRANSMITTER (THDLC) ........................................................................................................................................................... 79 3.16.1 E1 Mode ....................................................................................................................................................................................... 79 3.16.2 T1 / J1 Mode ................................................................................................................................................................................ 79 3.17 BIT-ORIENTED MESSAGE TRANSMITTER (TBOM) - T1 / J1 ONLY .................................................................................................... 80 3.18 INBAND LOOPBACK CODE GENERATOR (IBCG) - T1 / J1 ONLY ...................................................................................................... 80 |
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Similar Description - IDT82V2108 |
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