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Rev 0.5

Oct. 2004

K7R643684M

K7R641884M

Preliminary

The K7R643684M and K7R641884M are 75,497,472-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.

They are organized as 2,097,152 words by 36bits for K7R643684M and 4,194,304 words by 18 bits for K7R641884M.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports

with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram on every rising edge of K and K,

and transfered out of sram on every rising edge of C and C.

And totally independent read and write ports eliminate the need for high speed bus turn around.

Address for read and write are latched on alternate rising edges of the input clock K.

Data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read data are referenced to echo clock ( CQ or CQ ) outputs.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 4-bit sequential for both read and write operations, reguiring tow full clock bus cycles.

Any request that attempts to interrupt a burst operation in progress is ignored.

Synchronous pipeline read and late write enable high speed operations.

Simple depth expansion is accomplished by using R and W for port selection.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.

The K7R643684M and K7R641884M are implemented with SAMSUNG's high performance 6T CMOS technology

and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

The process continues until all four data are transfered.

Continuous read operations are initated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K insted of C and C.

When the R is disabled after a read operation,the K7R643684M and K7R641884M will first complete burst read operation

before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

Write cycles are initiated by activating W at the rising edge of the positive input clock K.

Address is presented and stored in the write address register synchronized with K clock.

For 4-bit burst DDR operation, it will write four 36-bit or 18-bit data words with each write command.

The first "late" data is transfered and registered in to the device synchronous with next K clock rising edge.

Next burst data is transfered and registered synchronous with following K clock rising edge.

The process continues until all four data are transfered and registered.

Continuous write operations are initated with K rising edge.

And "late writed" data is presented to the device on every rising edge of both K and K clocks.

The device disregards input data presented on the same cycle W disabled.

When the W is disabled after a read operation, the K7R643684M and K7R641884M will first complete burst read operation

before entering into deselect mode at the next K clock rising edge.

The K7R643684M and K7R641884M support byte write operations.

Write Operations