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LTC3831EGN Datasheet(PDF) 8 Page - Linear Technology |
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LTC3831EGN Datasheet(HTML) 8 Page - Linear Technology |
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8 / 20 page  8 LTC3831 3831f TEST CIRCUITS Figure 2 APPLICATIO S I FOR ATIO SS FREQSET FB COMP R+ NC NC VFB VCOMP 2.5V TG BG SHDN VCC VSHDN VCC PVCC2 PVCC1 PVCC IFB 6800pF 0.1 µF 10 µF TG RISE/FALL BG RISE/FALL 6800pF 3831 F02 R– IMAX GND LTC3831 PGND + OVERVIEW The LTC3831 is a voltage mode feedback, synchronous switching regulator controller (see Block Diagram) de- signed for use in high to medium power, DDR memory termination. It includes an onboard PWM generator, a ratiometric reference, two high power MOSFET gate driv- ers and all necessary feedback and control circuitry to form a complete switching regulator circuit. The PWM loop nominally runs at 200kHz. The LTC3831 is designed to generate an output voltage that tracks at 1/2 of the external voltage connected between the R+ and R– pins. The LTC3831 can be used to generate the termination voltage, VTT,forinterfaceliketheSSTL_2where VTT is a ratio of the interface supply voltage, VDDQ. It is a requirement in the SSTL_2 interface standard for VTT to track the interface supply voltage to improve noise immu- nity. Using the LTC3831 to supply the interface termina- tion voltage allows large current sourcing and sinking through the termination resistors during bus transitions. The LTC3831 includes a current limit sensing circuit that uses the topside external N-channel power MOSFET as a current sensing element, eliminating the need for an external sense resistor. Also included is an internal soft- start feature that requires only a single external capacitor to operate. In addition, the part features an adjustable oscillator which can free run or synchronize to an external signal with frequencies from 100kHz to 500kHz, allowing added flexibility in external component selection. THEORY OF OPERATION Primary Feedback Loop The LTC3831 senses the output voltage of the circuit through the FB pin and feeds this voltage back to the internal transconductance error amplifier, ERR. The error amplifier compares the output voltage to the internal ratiometric reference, VREF, and outputs an error signal to the PWM comparator. VREF is set to 0.5 multiplied by the voltage difference between the R+ and R– pins, using an internal resistor divider. This error signal is compared with a fixed frequency ramp waveform, from the internal oscillator, to generate a pulse width modulated signal. This PWM signal drives the external MOSFETs through the TG and BG pins. The resulting chopped waveform is filtered by LO and COUT which closes the loop. Loop compensation is achieved with an external compensation network at the COMP pin, the output node of the error amplifier. MIN, MAX Feedback Loops Two additional comparators in the feedback loop provide high speed output voltage correction in situations where the error amplifier may not respond quickly enough. MIN compares the feedback signal to a voltage 3% below VREF. If the signal is below the comparator threshold, the MIN comparator overrides the error amplifier and forces the loop to maximum duty cycle, >91%. Similarly, the MAX |
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