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LTC3830ES Datasheet(PDF) 11 Page - Linear Technology |
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LTC3830ES Datasheet(HTML) 11 Page - Linear Technology |
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11 / 24 page  11 LTC3830/LTC3830-1 sn3830 3830fs The LTC3830 internal oscillator can be externally synchro- nized from 100kHz to 500kHz. Frequencies above 300kHz can cause a decrease in the maximum obtainable duty cycle as rise/fall time and propagation delay take up a larger percentage of the switch cycle. Circuits using these frequencies should be checked carefully in applications where operation near dropout is important—like 3.3V to 2.5V converters. The low period of this clock signal must not be >100 µs, or else the LTC3830 enters shutdown mode. Figure 5 describes the operation of the external synchro- nization function. A negative transition at the SHDN pin forces the internal ramp signal low to restart a new PWM cycle. Notice that with the traditional sync method, the ramp amplitude is lowered as the external clock frequency goes higher. The effect of this decrease in ramp amplitude increases the open-loop gain of the controller feedback loop. As a result, the loop crossover frequency increases and it may cause the feedback loop to be unstable if the phase margin is insufficient. To overcome this problem, the LTC3830 monitors the peak voltage of the ramp signal and adjusts the oscillator charging current to maintain a constant ramp peak. Input Supply Considerations/Charge Pump The 16-lead LTC3830 requires four supply voltages to operate: VIN for the main power input, PVCC1 and PVCC2 for MOSFET gate drive and a clean, low ripple VCC for the LTC3830 internal circuitry (Figure 6). The LTC3830-1 and the 8-lead LTC3830 have the PVCC2 and VCC pins tied together inside the package (Figure 7). This pin, brought out as VCC/PVCC2 , has the same low ripple requirements as the 16-lead part, but must also be able to supply the gate drive current to Q2. In many applications, VCC can be powered from VIN through an RC filter. This supply can be as low as 3V. The low quiescent current (typically 800 µA) allows the use of relatively large filter resistors and correspondingly small APPLICATIO S I FOR ATIO SHDN 200kHz FREE RUNNING RAMP SIGNAL TRADITIONAL SYNC METHOD WITH EARLY RAMP TERMINATION LTC3830 KEEPS RAMP AMPLITUDE CONSTANT UNDER SYNC RAMP SIGNAL WITH EXT SYNC RAMP AMPLITUDE ADJUSTED 3830 F05 Figure 5. External Synchronization Operation 3830 F6 + VCC PVCC2 PVCC1 VIN G1 Q1 COUT VOUT Q2 LO G2 INTERNAL CIRCUITRY LTC3830 (16-LEAD) 3830 F7 + VCC/PVCC2 PVCC1 VIN G1 Q1 COUT VOUT Q2 LO G2 INTERNAL CIRCUITRY LTC3830 (8-LEAD) Figure 6. 16-Lead Power Supplies Figure 7. 8-Lead Power Supplies |
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