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M29F102BB55N1F Datasheet(PDF) 4 Page - STMicroelectronics |
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M29F102BB55N1F Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 24 page M29F102BB 4/24 SUMMARY DESCRIPTION The M29F102BB is a 1 Mbit (64Kb x16) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single 5V supply. On power-up the memo- ry defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are writ- ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically ar- ranged, see Table 2., Bottom Boot Block Address- es, M29F102BB. The first 32 Kwords have been divided into four additional blocks. The 8 Kword Boot Block can be used for small initialization code to start the microprocessor, the two 4 Kword Pa- rameter Blocks can be used for parameter storage and the remaining 16 Kwords are a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in PLCC44 and TSOP40 (10 x 14mm) packages. In addition to the standard version, the packages are also available in Lead- free version, in compliance with JEDEC Std J- STD-020B, the ST ECOPACK 7191395 Specifica- tion, and the RoHS (Restriction of Hazardous Sub- stances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to ’1’). Figure 2. Logic Diagram Table 1. Signal Names Table 2. Bottom Boot Block Addresses, M29F102BB A0-A15 Address Inputs DQ0-DQ15 Data Inputs/Outputs E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect VCC Supply Voltage VSS Ground NC Not Connected Internally AI02130C 16 A0-A15 W DQ0-DQ15 VCC M29F102BB E VSS 16 G RP # Size (KWords) Address Range 4 32 8000h-FFFFh 3 16 4000h-7FFFh 2 4 3000h-3FFFh 1 4 2000h-2FFFh 0 8 0000h-1FFFh |
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