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AD9690 Datasheet(PDF) 10 Page - Analog Devices |
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AD9690 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 79 page  Data Sheet AD9690 Rev. B | Page 9 of 78 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 3 tSU_SR Device clock to SYSREF+ setup time 117 ps tH_SR Device clock to SYSREF+ hold time −96 ps SPI TIMING REQUIREMENTS See Figure 4 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns tLOW Minimum period that SCLK must be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 4) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 4) 10 ns Timing Diagrams SERDOUT0– N – 54 N – 53 N – 52 N – 51 N – 1 SAMPLE N N + 1 APERTURE DELAY N – 55 CLK+ CLK– CLK+ CLK– SERDOUT0+ SERDOUT1– SERDOUT1+ A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB CONVERTER0 LSB ANALOG INPUT SIGNAL SAMPLE N – 55 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 54 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 53 ENCODED INTO 1 8-BIT/10-BIT SYMBOL Figure 2. Data Output Timing (Full Bandwidth Mode; L = 2; M = 1; F = 1) CLK+ CLK– SYSREF+ SYSREF– tSU_SR tH_SR Figure 3. SYSREF± Setup and Hold Timing |
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