PC107A datasheet(3/50 Pages) ATMEL

Part #	PC107A

Description	PCI Bridge Memory Controller

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Manufacturer	ATMEL [ATMEL Corporation]

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PC107A [Preliminary]

2137C–HIREL–03/04

General Parameters

The following list provides a summary of the general parameters of the PC107A:

Technology

0.29 µm CMOS, five-layer metal

Die size

50 mm

2

Transistor count

0.96 million

Logic design

Fully-static

Package

Surface mount 503 Plastic Ball Grid Array (C4/PBGA)

Core power supply

2.5 ±5% V DC (nominal; see Table 3 on page 12 for

recommended operating conditions)

I/O power supply

3.0 to 3.6V DC

Features

The PC107A provides an integrated high-bandwidth, high-performance interface

between up to two 60x processors, the PCI bus, and main memory. This section sum-

marizes the features of the PC107A. Major features of the PC107A are as follows:

•

Memory Interface

–

64-/32-bit 100 MHz bus

–

Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM

–

High-bandwidth bus (32-/64-bit data bus) to DRAM

–

Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices,

and up to four banks of 256 Mbit SDRAM devices

–

Supports 1M byte to 1 Gbyte DRAM memory

–

144M bytes of ROM space

–

8-, 32-, or 64-bit ROM

–

Write buffering for PCI and processor accesses

–

Supports normal parity, read-modify-write (RMW), or ECC

–

Data-path buffering between memory interface and processor

–

Low-voltage TTL logic (LVTTL) interfaces

–

Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller

interface with programmable address strobe timing

•

32-bit PCI Interface Operating up to 66 MHz

–

PCI 2.1-compliant

–

PCI 5.0V tolerance

–

Support for PCI locked accesses to memory

–

Support for accesses to PCI memory, I/O, and configuration spaces

–

Selectable big- or little-endian operation

–

Store gathering of processor-to-PCI write and PCI-to-memory write

accesses

–

Memory prefetching of PCI read accesses

–

Selectable hardware-enforced coherency

–

PCI bus arbitration unit (five request/grant pairs)

–

PCI agent mode capability

–

Address translation unit

–

Some internal configuration registers accessible from PCI

•

Two-channel Integrated DMA Controller (Writes to ROM/Port × Not Supported)

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