SN54HC595, SN74HC595

8BIT SHIFT REGISTERS

WITH 3STATE OUTPUT REGISTERS

SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004

7

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

SN54HC595

SN74HC595

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

6

4.2

5

fclock

Clock frequency

4.5 V

31

21

25

MHz

fclock

Clock frequency

6 V

36

25

29

MHz

2 V

80

120

100

SRCLK or RCLK high or low

4.5 V

16

24

20

tw

Pulse duration

SRCLK or RCLK high or low

6 V

14

20

17

ns

tw

Pulse duration

2 V

80

120

100

ns

SRCLR low

4.5 V

16

24

20

SRCLR low

6 V

14

20

17

2 V

100

150

125

SER before SRCLK

↑

4.5 V

20

30

25

SER before SRCLK

↑

6 V

17

25

21

2 V

75

113

94

SRCLK

↑ before RCLK↑†

4.5 V

15

23

19

tsu

Setup time

SRCLK

↑ before RCLK↑†

6 V

13

19

16

ns

tsu

Setup time

2 V

50

75

65

ns

SRCLR low before RCLK

↑

4.5 V

10

15

13

SRCLR low before RCLK

↑

6 V

9

13

11

2 V

50

75

60

SRCLR high (inactive) before SRCLK

↑

4.5 V

10

15

12

SRCLR high (inactive) before SRCLK

↑

6 V

9

13

11

2 V

0

0

0

th

Hold time, SER after SRCLK

↑

4.5 V

0

0

0

ns

th

Hold time, SER after SRCLK

6 V

0

0

0

ns

† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift

register is one clock pulse ahead of the storage register.