Preliminary W583XXX

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Pin Description only for W583S15 to W583M02, continued

NAME

I/O

DESCRIPTION

TG8

I

Direct trigger input 8, internally pulled high

STPF

O

Stop signal F

STPG

O

Stop signal G

STPH

O

Stop signal H

Pin Description only for W583S10

NAME

I/O

DESCRIPTION

OSC

I

Ring oscillator input

OSCO

O

Oscillator clock output

FUNCTIONAL DESCRIPTION

The W583xxx is a derivative of Winbond's PowerSpeech

 synthesizers, which are becoming

dominant in the consumer market, especially for toy applications.

There are up to 8 trigger inputs and 8 STOP outputs in W583xxx. The maximal number of software

key pad by scanning matrix is up to 8

× 9 = 72 keys. There are 8 general purpose registers, R0-R7.

R0-R7 can apply not only for "LD" and "JP" instructions but also for "MV" instruction. Only R0 can

apply for "INC" instruction. CPU interface is the same as the W581xx series.

IR interface is a new feature of PowerSpeech

. User can use IR interface to transmit and receive a

command. For example, when X chip executes the "TX R1" instruction, the Pulse Position Modulation

waveform (with 38 KHz carrier) outputs from IROUT pin to drive a photo diode. Y chips within a

certain distance will receive the IR signal through an IR receiver module to TG3/IRIN pin and execute

a "JP" instruction to the interrupt vector/label pointed by R1 of X chip.

There are two kinds of events that can cause the W583xxx to enter the POI (Power On Initialization)

process: one is power on, and the other is direct trigger from RESET pin. The interrupt vector "32" is

allocated for this special event, and its priority is above all, i.e., no triggers can override the POI

process if they all happen simultaneously. So the user can write a program into this interrupt vector to

set the power on initial state. If the user does not wish to execute a program on power on, he should

write an "END" instruction in interrupt vector "32". During the POI process, triggers can then override

it successfully; if the EN0, EN1 and MODE0, MODE1 registers are set properly.

If more than two events happen simultaneously, the priority that is set by the internal H/W is: POI >

TG1F > TG1R > TG2F > TG2R > TG3F > TG3R > TG4F > TG4R > TG5F > TG5R > TG6F > TG6R

> TG7F > TG7R > TG8F > TG8R > "JP" instruction.