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XRD8775AID Datasheet(PDF) 6 Page - Exar Corporation |
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XRD8775AID Datasheet(HTML) 6 Page - Exar Corporation |
6 / 15 page XRD8775 6 Rev. 4.00 APPLICATION NOTES Signals should not exceed AV DD +0.5V or go below AGND -0.5V or DV DD +0.5V or DGND -0.5V. All pins have internal protection diodes that will protect them from short transients (<100 µs) outside the supply range. AGND and DGND pins are connected internally through the P- substrate. DC voltage differences between these pins will cause undesirable internal substrate currents. The power supply (AV DD) and reference voltage (VRT & V RB) pins should be decoupled with 0.1µF and 10µF capacitors to AGND, placed as close to the chip as possible. The digital outputs should not drive long wires or buses. The capacitive coupling and reflections will contribute noise to the conversion. To avoid timing errors, use the rising edge of the sample clock (CLK) to latch data from the XRD8775 to other parts of the system. The reference can be biased internally by shorting V RT to V RTS and VRB to VRBS. This will generate 0.6V at VRB and 2.6V at V RT (see Figure 5.). If the internal reference pins V RTS and/or VRBS are not used they should be left unconnected. Graph 1. DNL vs. Code -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 Code Vdd = 5.0V Vrt = 2.6V Vrb = 0.6V Fs = 15MHz Ta = 25 oC |
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