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AD9633BCPZ-125 Datasheet(PDF) 8 Page - Analog Devices |
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AD9633BCPZ-125 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 42 page  Data Sheet AD9633 Rev. B | Page 7 of 41 TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 1.2 ns min tHSYNC SYNC to rising edge of CLK+ hold time −0.2 ns min SPI TIMING REQUIREMENTS See Figure 73 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 73) 10 ns min tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 73) 10 ns min Timing Diagrams Refer to the Memory Map Register Descriptions section and Table 21 for SPI register settings. D0–A D0+A D1–A D1+A FCO– BYTEWISE MODE FCO+ D0–A D0+A D1–A D1+A FCO– DCO– CLK+ CLK– DCO+ FCO+ BITWISE MODE SDR DDR DCO– DCO+ D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 MSB N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 MSB N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 LSB N – 17 MSB N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D07 N – 16 D06 N – 16 MSB N – 17 D10 N – 17 D09 N – 17 D08 N – 17 D07 N – 17 D06 N – 17 tEH tCPD tFRAME tFCO tPD tDATA tLD VIN±x tA N – 1 N N + 1 tEL Figure 2. 12-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default) |
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