54HC4050RPFE datasheet(4/8 Pages) ETC

Part #	54HC4050RPFE

Description	CMOS Logic Hex Non-Inverting Buffers

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CMOS Logic Hex Non-Inverting Buffers

54HC4050

12.19.01 Rev 1

1000587

Quiescent Device Current

I

CC

V

I = VCC or GND, IO = 0mA

V

CC = 6V

+25°C

--

2

µA

-55 to 125°C

--

40

TABLE 6. 54HC4050 AC ELECTRICAL CHARACTERISTICS

(V

CC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)

PARAMETER

SYMBOL

TEST CONDITION

MIN

MAX

UNIT

Propogation Delay

nA to nY

t

PLH, tPHL

C

L = 50pF

V

CC = 2V

+25°C

--

85

ns

-55 to 125°C

--

130

V

CC = 4.5V

+25°C

--

17

-55 to 125°C

--

26

V

CC = 6V

+25°C

--

14

-55 to 125°C

--

22

Transition Times

(Figure 1)

t

TLH, tTHL

C

L = 50pF

V

CC = 2V

+25°C

--

75

ns

-55 to 125°C

--

110

V

CC = 4.5V

+25°C

--

15

-55 to 125°C

--

22

V

CC = 6V

+25°C

--

13

-55 to 125°C

--

19

TABLE 7. 54HC4050 CAPACITANCE1

1. Guaranteed by design.

PARAMETER

SYMBOL

TEST CONDITIONS

MAX

UNIT

Input Capacitance

C

I

10

pF

Power Dissipation Capacitance2, 3

2. C

PD is used to determine the dynamic power consumption, per gate.

3. P

D = VCC

2

fi (C

PD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

C

PD

V

CC = 5V

35

pF

TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS

(V

CC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

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