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AT40K10-2RQC Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT40K10-2RQC Datasheet(HTML) 10 Page - ATMEL Corporation |
10 / 67 page 10 AT40K/AT40KLV Series FPGA 0896C–FPGA–04/02 Figure 6. Some Single Cell Modes DQ DQ Q Q (Registered) DQ DQ Synthesis Mode. This mode is particularly important for the use of VHDL/Verilog design. VHDL/Verilog Synthesis tools generally will produce as their output large amounts of random logic functions. Having a 4-input LUT structure gives efficient random logic optimization without the delays associated with larger LUT structures. The output of any cell may be registered, tri-stated and/or fed back into a core cell. Arithmetic Mode is frequently used in many designs. As can be seen in the figure, the AT40K/AT40KLV core cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the sum output in this diagram is registered. This output could then be tri-stated and/or fed back into the cell. DSP/Multiplier Mode. This mode is used to efficiently implement array multipliers. An array multiplier is an array of bitwise multipliers, each implemented as a full adder with an upstream AND gate. Using this AND gate and the diagonal interconnects between cells, the array multiplier structure fits very well into the AT40K/AT40KLV architecture. Counter Mode. Counters are fundamental to almost all digital designs. They are the basis of state machines, timing chains and clock dividers. A counter is essentially an increment by one function (i.e., an adder), with the input being an output (or a decode of an output) from the previous stage. A 1-bit counter can be implemented in one core cell. Again, the output can be registered, tri-stated and/or fed back. Tri-state/Mux Mode. This mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. The output of the core cell is very often tri-statable for many inputs to many outputs data switching. A B C D A B C A B C D A B C EN Q Q SUM (Registered) SUM and/or PRODUCT or CARRY PRODUCT (Registered) CARRY CARRY CARRY IN and/or or and/or and/or |
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