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AD9254BCPZ-150 Datasheet(PDF) 7 Page - Analog Devices |
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AD9254BCPZ-150 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 41 page  AD9254 Rev. 0 | Page 6 of 40 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted. Table 4. AD9254BCPZ-150 Parameter1 Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Full 20 150 MSPS Conversion Rate, DCS Disabled Full 10 150 MSPS CLK Period Full 6.7 ns CLK Pulse Width High, DCS Enabled Full 2.0 3.3 4.7 ns CLK Pulse Width High, DCS Disabled Full 3.0 3.3 3.7 ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD)2 Full 3.1 3.9 4.8 ns DCO Propagation Delay (tDCO) Full 4.4 ns Setup Time (tS) Full 1.9 2.9 ns Hold Time (tH) Full 3.0 3.8 ns Pipeline Delay (Latency) Full 12 Cycles Aperture Delay (tA) Full 0.8 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms Wake-Up Time3 Full 350 μs OUT-OF-RANGE RECOVERY TIME Full 3 Cycles SERIAL PORT INTERFACE4 SCLK Period (tCLK) Full 40 ns SCLK Pulse Width High Time (tHI) Full 16 ns SCLK Pulse Width Low Time (tLO) Full 16 ns SDIO to SCLK Setup Time (tDS) Full 5 ns SDIO to SCLK Hold Time (tDH) Full 2 ns CSB to SCLK Setup Time (tS) Full 5 ns CSB to SCLK Hold Time (tH) Full 2 ns 1 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. 3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB. 4 See Figure 50 and the Serial Port Interface (SPI) section. TIMING DIAGRAM CLK+ DCO DATA N N+ 1 N+ 2 N+ 3 N+ 4 N+ 5 N+ 6 N+ 7 N+ 8 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 13 CLK– tCLK tPD tS tH tDCO tCLK tA Figure 2. Timing Diagram |
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